MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 206

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.5.2.3
SCCR, shown in
Table 4-36
4-40
Address 0x0_0A08
10–11
12–14
Bits
0–1
4–5
6–7
8–9
Reset
Reset
2
3
W
W
R
R
TSECCM
TSEC1ON
TSEC2ON
16
0
1
TSECCM
0
ENCCM
defines the bit fields of SCCR.
DRCM
Name
USB
—
—
—
System Clock Control Register (SCCR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
1
1
Figure
TSEC
1ON
TSEC1 and TSEC2 clock mode.
00 Reserved. Write not allowed. If written, treated as ratio 1:1.
01 TSEC1&2 clock/ csb_clk ratio is 1:1.
10 TSEC1&2 clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than TSEC1&2).
11 TSEC1&2 clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than TSEC1&2).
TSEC1 clock switch off
0 TSEC1 clock is disabled.
1 TSEC1 clock is enabled and in the ratio as specified by TSECCM.
TSEC2 clock switch off
0 TSEC2 clock is disabled.
1 TSEC2 clock is enabled and in the ratio as specified by TSECCM.
Reserved
Encryption core and I
00 Encryption core clock is disabled.
01 Encryption core clock/ csb_clk ratio is 1:1.
10 Encryption core clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the encryption core).
11 Encryption core clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the encryption core).
Reserved
USB DR clock mode.
00 USB DR clock is disabled.
01 USB DR clock/ csb_clk ratio is 1:1.
10 USB DR clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the USB DR).
Note: 11USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR).
Reserved
1
1
2
4-15, controls device units that have a configurable clock ratio.
TSEC2
Figure 4-15. System Clock Control Register (SCCR)
ON
1
1
3
Table 4-36. SCCR Bit Descriptions
1
1
4
2
—
C1 clock mode.
1
1
5
ENCCM
6
0
1
1
1
7
—
Description
8
1
1
—
1
1
9
USBDRCM
10
0
1
11
1
1
12
1
1
Freescale Semiconductor
—
Access: Read/Write
1
1
14
1
1
PCICM
15
31
1
1