MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 794
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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15.5.3.5.11 MII Management Indicator Register (MIIMIND)
The MIIMIND register is read-only by the user.
register.
15.5.3.5.12 Interface Status Register (IFSTAT)
Figure 15-47
Table 15-51
15-76
Offset eTSEC1:0x2_453C; eTSEC2:0x2_553C
Reset
0–21
Bits
W
R
Offset eTSEC1:0x2_4534
Reset
0
0–28
W
Bits
R
29
30
31
0
Name
describes the fields of the FSTAT register.
shows the IFSTAT register.
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Not Valid Not valid.
Name
Scan
Busy
—
Reserved
Reserved
0 MII Mgmt read cycle has completed and the read data is valid.
1 MII Mgmt read cycle has not completed and the read data is not yet valid.
Scan in progress.
0 A scan operation (continuous MII Mgmt read cycles) is not in progress.
1 A scan operation (continuous MII Mgmt read cycles) is in progress.
Busy.
0 MII Mgmt block is not currently performing an MII Mgmt read or write cycle.
1 MII Mgmt block is currently performing an MII Mgmt read or write cycle.
Figure 15-46. MII Mgmt Indicator Register Definition
Figure 15-47. Interface Status Register Definition
Table 15-50. MIIMIND Field Descriptions
Table 15-51. IFSTAT Field Descriptions
—
—
Figure 15-46
All zeros
All zeros
Description
Description
describes the definition for the MIIMIND
21
Excess Defer
22
28
Not Valid
23
29
Freescale Semiconductor
Access: Read only
Access: Read only
—
Scan
30
Busy
31
31
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