MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 55
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Freescale Semiconductor
Acronyms and Abbreviated Terms...................................................................................... lxxvii
Supported eTSEC1 and eTSEC2 Configurations ................................................................. 1-12
Memory Map........................................................................................................................... 2-2
MPC8313E Signal Reference by Functional Block................................................................ 3-3
Reset Configuration Signals.................................................................................................. 3-12
Output Signal States During System Reset ........................................................................... 3-13
Signals for Multiplexing ....................................................................................................... 3-14
External Signals—Detailed Signal Descriptions .................................................................. 3-14
System Control Signals ........................................................................................................... 4-1
External Clock Signals............................................................................................................ 4-3
Reset Causes ........................................................................................................................... 4-5
Reset Actions .......................................................................................................................... 4-6
Reset Configuration Words Source....................................................................................... 4-10
SYS_CLK_IN Division ........................................................................................................ 4-11
Selecting Reset Configuration Input Signals ........................................................................ 4-11
RCWLR Bit Settings............................................................................................................. 4-13
System PLL Ratio ................................................................................................................. 4-14
SPMF Maximum Values ....................................................................................................... 4-14
Reset Configuration Word High Bit Settings........................................................................ 4-15
PCI Host/Agent Configuration.............................................................................................. 4-16
Boot Memory Space.............................................................................................................. 4-17
Boot Sequencer Configuration.............................................................................................. 4-17
Boot ROM Location.............................................................................................................. 4-18
eTSEC1 Mode Configuration ............................................................................................... 4-19
eTSEC2 Mode Configuration ............................................................................................... 4-20
e300 Core True Little-Endian ............................................................................................... 4-20
LALE Configuration ............................................................................................................. 4-21
Local Bus Configuration EEPROM Addresses .................................................................... 4-21
Local Bus Reset Configuration Words Data Structure.......................................................... 4-21
Local Bus Controller Setting When Loading RCW.............................................................. 4-22
Hard Coded Reset Configuration Word Low Fields Values ................................................. 4-26
Hard-Coded Reset Configuration Word High Field Values .................................................. 4-27
Examples For Hard-Coded Reset Configuration Words Usage............................................ 4-27
Configurable Clock Units ..................................................................................................... 4-31
Reset Configuration and Status Registers Memory Map...................................................... 4-32
Reset Status Register Field Descriptions .............................................................................. 4-33
RMR Field Descriptions ....................................................................................................... 4-35
RPR Bit Descriptions ............................................................................................................ 4-36
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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