MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 601

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.3.2.5
PCI_EACR contains fields for storing the low portion of the address associated with the first PCI error
captured.
Table 13-12
Freescale Semiconductor
10–11
12–15
16–19
20–23
24–27
28–29
Offset 0x10
Reset
Bits
8–9
30
31
0–31
Bits
W
R
0
Name
CMD
Figure 13-9
ES
BE
PB
TS
—
—
—
VI
describes the bit settings of the PCI_EACR register.
PCI Error Address Capture Register (PCI_EACR)
PCI_EA
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Reserved
Transaction size. Indicates the size of the transaction in units of doublewords (8 bytes). If the transaction
crossed a cache line (32-byte) boundary, this field indicates the number of actual double words in the cache
line on which the error occurred. This field is valid only if the PCI controller was the master of the
transaction.
00 4 double words
01 1 double word
10 2 double words
11 3 double words
Error source. This field indicates the source of the PCI transaction.
0000 External master
0101 DMA
Others reserved
PCI command. Contains the PCI command PCI_CBE[3:0] of the transaction.
Reserved
PCI byte enables. Contains the PCI byte enables PCI_CBE[3:0] for the data word.
Reserved
Parity bit. Contains the PCI parity bit for the captured data word.
Error information valid. This bit indicates that the error information captured in this register, PCI_EACR,
PCI_EEACR, and PCI_EDCR is valid.
0 No valid error information
1 Error information is valid
shows the PCI_EACR fields.
Figure 13-9. PCI Error Address Capture Register (PCI_EACR)
PCI error address. Contains the low portion of the address associated with the first detected error.
Read only.
Table 13-11. PCI_EATCR Field Descriptions (continued)
Table 13-12. PCI_EACR Field Description
All zeros
PCI_EA
Description
Description
Access: Read only
PCI Bus Interface
13-19
31