MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 499
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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CSNT = 1, LWE
LCRR[CLDIV] = 2, LWE
If LCRR[CLKDIV] = 2, LCSn and LWEn are negated either normally or one cycle earlier if TRLX = 1.
For example, when ACS = 00, CSNT = 1 and TRLX = 0, LWEn is negated one quarter of a clock earlier
and LCSn is negated normally as shown in
10.4.2.3.3
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
Figure 10-37
LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to
the ACS = 11 case. The example in
pair of writes issued consecutively.
Freescale Semiconductor
1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWE
2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal
3. TRLX = 1 in conjunction with CSNT = 1, negates the LCSn and LWE
•
•
•
•
•
independent of ACS.
case provided that LCRR[CLDIV] = 4 or 8.
LCRR[CLKDIV] = 4 or 8.
An additional bus cycle is added between the address and control signals (but only if ACS is not
equal to 00).
The number of wait states specified by SCY is doubled, providing up to 30 wait states.
The extended hold time on read accesses (EHTR) is extended further.
LCSn signals are negated one cycle earlier during writes (but only if ACS is not equal to 00).
LWE[0:1] signals are negated one cycle earlier during writes.
and
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Relaxed Timing
n
Figure 10-38
is negated one quarter of a clock earlier, as shown in
n
is negated either coincident with LCSn or one cycle earlier.
show relaxed timing read and write transactions. The effect of
Figure 10-38
Figure
also shows address and data multiplexing on LAD for a
10-36.
Figure
n
10-36. If
1+1/4 cycle earlier if
Enhanced Local Bus Controller
n
is affected
10-51
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