MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 749

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.1.6
ECNTRL is a register writable by the user to reset, configure, and initialize the eTSEC. Note that the
FIFM, GMIIM, RPM, and RMM fields are read-only, having been set after sampling signals at
power-on-reset. (Refer to the TSEC mode
(RCWHR)”).
Figure 15-7
Table 15-11
Freescale Semiconductor
Offset eTSEC1:0x2_4020; eTSEC2:0x2_5020
Reset
Reset
Bits
30
31
0–15
Bits
16
17
18
W
W
R
R FIFM
16
0
PERRDIS
DPEDIS
CLRCNT Clear all statistics counters
Name
AUTOZ
Name
describes the definition for the ECNTRL register.
FIFM
CLRCNT AUTOZ STEN
describes the fields of the ECNTRL register.
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Ethernet Control Register (ECNTRL)
17
Data parity error disable.
0 Allow eTSEC to report IEVENT[DPE] status.
1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays.
Receive frame parse error disable.
0 Allow eTSEC to report IEVENT[PERR] status.
1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
Reserved
FIFO mode. Not supported.
0 Allow MIB counters to continue to increment.
1 Reset all MIB counters.
This bit is self-resetting.
Automatically zero MIB counter values.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
18
Table 15-10. EDIS Field Descriptions (continued)
19
Figure 15-7. ECNTRL Register Definition
Table 15-11. ECNTRL Field Descriptions
20
inSection 4.3.2.2, “Reset Configuration Word High Register
—
All zeros
All zeros
—
24
Description
Description
GMIIM TBIM RPM
25
26
Enhanced Three-Speed Ethernet Controllers
27
R100M
28
RMM SGMIIM
29
Access: Mixed
30
15-31
—
15
31