MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 18
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Paragraph
Number
12.3.7
12.3.8
12.3.8.1
12.3.8.2
12.3.8.3
12.3.8.4
12.3.8.5
12.3.8.6
12.3.8.7
12.3.8.8
12.4
12.4.1
12.4.1.1
12.4.1.2
12.4.2
12.4.3
12.4.3.1
12.4.3.2
12.4.4
12.4.4.1
12.4.4.2
12.5
12.5.1
12.5.2
13.1
13.1.1
13.1.2
13.1.2.1
13.1.2.2
13.2
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.2
13.3.2.1
xviii
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional Description................................................................................................. 12-15
Initialization/Application Information ......................................................................... 12-20
Introduction.................................................................................................................... 13-1
External Signal Description ........................................................................................... 13-4
Memory Map/Register Definitions .............................................................................. 13-11
Inbound Message Interrupt Mask Register (IMIMR)................................................ 12-8
DMA Registers .......................................................................................................... 12-9
Message Unit ........................................................................................................... 12-15
DMA Controller....................................................................................................... 12-16
DMA Operation ....................................................................................................... 12-16
DMA Segment Descriptors...................................................................................... 12-18
Initialization Steps in Direct Mode.......................................................................... 12-20
Initialization Steps in Chaining Mode ..................................................................... 12-20
Features...................................................................................................................... 13-3
Modes of Operation ................................................................................................... 13-3
PCI Configuration Access Registers........................................................................ 13-12
PCI Memory-Mapped Control and Status Registers ............................................... 13-15
DMA Mode Register (DMAMRn) ........................................................................ 12-9
DMA Status Register (DMASRn) ....................................................................... 12-11
DMA Current Descriptor Address Register (DMACDARn) .............................. 12-12
DMA Source Address Register (DMASARn)..................................................... 12-13
DMA Destination Address Register (DMADARn)............................................. 12-13
DMA Byte Count Register (DMABCRn) ........................................................... 12-14
DMA Next Descriptor Address Register (DMANDARn)................................... 12-14
DMA General Status Register (DMAGSR)......................................................... 12-15
Messaging Registers (IMR0–IMR1, OMR0–OMR1) ......................................... 12-15
Doorbell Registers (IDR and ODR) .................................................................... 12-16
DMA Coherency.................................................................................................. 12-17
Halt and Error Conditions.................................................................................... 12-17
Descriptor in Big-Endian Mode........................................................................... 12-19
Host/Agent Mode Configuration ........................................................................... 13-3
PCI Arbiter Configuration ..................................................................................... 13-4
PCI_CONFIG_ADDRESS .................................................................................. 13-13
PCI_CONFIG_DATA.......................................................................................... 13-14
PCI Interrupt Acknowledge Register (PCI_INT_ACK)...................................... 13-15
PCI Error Status Register (PCI_ESR) ................................................................. 13-15
Descriptor in Little-Endian Mode........................................................................ 12-20
PCI Bus Interface
Contents
Chapter 13
Title
Freescale Semiconductor
Number
Page
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