MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 378
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Integrated Programmable Interrupt Controller (IPIC)
Table 8-18
8.5.11
Each bit in the system external interrupt mask register (SEMSR), shown in
external interrupt source. The user masks an interrupt by clearing the corresponding SEMSR bit. An
interrupt is unmasked (enabled) by setting the corresponding SEMSR bit.
When an external interrupt request occurs, the corresponding SEPNR bit is set regardless of the setting of
the corresponding SEMSR bit. However, if the corresponding SEMSR bit is cleared, no interrupt request
is passed to the core.
When an SEMSR bit is cleared by the user at the same time that an interrupt source requests an interrupt
service, the request stops. If the user sets the SEMSR bit later, a previously pending interrupt request is
processed by the core according to its assigned priority. SEMSR can be read by the user at any time.
Reset
Reset
8-20
12–15,
16–27
28–31
3–11,
Bits
0–2
W
W
R
R
1
2
SIRQ0
IRQ0
MIXB n P MIXB n priority order. Defines which interrupt source asserts its request in the MIXB n priority position. The
16
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
The user should drive all IRQ inputs to an inactive state prior to reset negation
0
Name
—
The reset values of implemented bits reflect the values of the external IRQ signals. Reserved bits are zeros.
1
defines the bit fields of SMPRR_B.
System External Interrupt Mask Register (SEMSR)
IRQ1 IRQ2 IRQ3 IRQ4
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
17
1
user must not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of MIXB n P is as follows:
000 RTC ALR asserts its request to the MIXB n position.
001 MU asserts its request to the MIXB n position.
010 SBA asserts its request to the MIXB n position.
011 DMA asserts its request to the MIXB n position.
100 IRQ4 asserts its request to the MIXB n position.
101–111Reserved
Write ignored, read = 0
2
Figure 8-14. System External Interrupt Mask Register (SEMSR)
3
Table 8-18. SMPRR_B Field Descriptions
4
5
All zeros
Description
—
—
Figure
8-11, corresponds to an
Freescale Semiconductor
Access: Read/write
2
15
31
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