MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 423
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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9.4.1.17
The DDR IP block revision 2 register, shown in
integration and configuration options.
Table 9-23
9.5
The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides
support for JEDEC-compliant DDR2 and DDR SDRAMs. The memory system allows a wide range of
memory devices to be mapped to any arbitrary chip select, and support is provided for registered DRAM
modules and unbuffered DRAM modules. However, registered DRAM modules cannot be mixed with
unbuffered DRAM modules.
Figure 9-19
internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and
column addresses. The transaction is compared with values in the row open table to determine if the
address maps to an open page. If the transaction does not map to an open page, an active command is
issued.
The memory interface supports as many as two physical banks of 32-bit wide memory. Bank sizes up to
512 Mbytes are supported, providing up to a maximum of 512 Mbytes of DDR main memory.
Programmable parameters allow for a variety of memory organizations and timings. The controller allows
as many as 16 pages to be open simultaneously. The amount of time (in clock cycles) the pages remain
open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
Freescale Semiconductor
16–23
24–31
8–15
Bits
0–7
Offset 0xBFC
Reset 0
W
R
IP_CFG IP block configuration options
IP_INT
Name
Functional Description
0
—
—
describes the DDR_IP_REV2 fields.
is a high-level block diagram of the DDR memory controller. Requests are received from the
0
DDR IP Block Revision 2 (DDR_IP_REV2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
Reserved
IP block integration options
Reserved
0 0
—
Figure 9-18. DDR IP Block Revision 2 (DDR_IP_REV2)
0
Table 9-23. DDR_IP_REV2 Field Descriptions
0 0
7
n
8
n n n n n n n 0 0 0 0 0 0 0 0 n n n n n n n n
IP_INT
Figure
9-18, provides read-only fields with the IP block
Description
15 16
—
23 24
Access: Read Only
DDR Memory Controller
IP_CFG
31
9-29
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