MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 526
MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
10.4.4.4
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in
at the bottom of the figure are UPM outputs. The selected LCSn is for the bank that matches the current
address. The selected LBS is for the byte lanes read or written by the access.
10-78
Clock Phases
T1, T2, T3, T4
Current Bank
LCLK
LCLK
RAM Array
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
T1
T2
T3
T4
T1
T2
T3
T4
LCS[0:3]
Figure 10-62. UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8
Selector
CS Line
Figure 10-61. UPM Clock Scheme for LCRR[CLKDIV] = 2
Figure 10-63. RAM Array and Signal Generation
LGPL0
External Signals Timing Generator
LGPL1
RAM Array
LGPL2 LGPL3 LGPL4 LGPL5
32 Bits
LBS[0:1]
Byte Select
64 deep
Logic
Figure
BRn[PS], LA[24:25]
Freescale Semiconductor
10-63. The signals
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