MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 20
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Paragraph
Number
13.3.3.28
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2
13.4.3
13.4.3.1
13.4.3.2
13.4.3.3
13.4.3.4
13.4.3.5
13.4.3.6
13.4.3.7
13.4.3.8
13.4.4
13.4.4.1
13.4.4.2
13.4.4.3
13.4.4.4
13.4.4.5
13.4.4.6
13.4.4.7
13.4.5
13.4.5.1
13.4.5.2
13.4.6
13.4.7
13.5
13.5.1
13.5.2
14.1
14.1.1
14.1.2
14.1.2.1
xx
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional Description................................................................................................. 13-43
Initialization/Application Information ......................................................................... 13-60
SEC 2.2 Architecture Overview .................................................................................... 14-2
PCI Bus Arbitration ................................................................................................. 13-43
Bus Commands ........................................................................................................ 13-46
PCI Protocol Fundamentals ..................................................................................... 13-47
Other Bus Operations............................................................................................... 13-53
Error Functions ........................................................................................................ 13-57
PCI Inbound Address Translation............................................................................ 13-59
CompactPCI Hot Swap Specification Support ........................................................ 13-60
Initialization Sequence for Host Mode .................................................................... 13-60
Initialization Sequence for Agent Mode.................................................................. 13-60
Descriptors ................................................................................................................. 14-3
Execution Units (EUs) ............................................................................................... 14-5
PCI Power Management Register 1 (PCIPMR1) ................................................ 13-42
Bus Parking.......................................................................................................... 13-44
Arbitration Algorithm.......................................................................................... 13-44
Broken Master Lock-Out ..................................................................................... 13-45
Master Latency Timer.......................................................................................... 13-45
Basic Transfer Control......................................................................................... 13-47
Addressing ........................................................................................................... 13-47
Device Selection .................................................................................................. 13-48
Byte Enable Signals............................................................................................. 13-48
Bus Driving and Turnaround ............................................................................... 13-48
Bus Transactions.................................................................................................. 13-49
Read and Write Transactions ............................................................................... 13-49
Transaction Termination ...................................................................................... 13-51
Fast Back-to-Back Transactions .......................................................................... 13-53
Dual Address Cycles............................................................................................ 13-54
Data Streaming .................................................................................................... 13-54
Host Mode Configuration Access........................................................................ 13-54
Agent Mode Configuration Access ..................................................................... 13-55
Special Cycle Command...................................................................................... 13-55
Interrupt Acknowledge ........................................................................................ 13-56
Parity.................................................................................................................... 13-57
Error Reporting.................................................................................................... 13-57
Data Encryption Standard Execution Unit (DEU)................................................. 14-5
Security Engine (SEC) 2.2
Contents
Chapter 14
Title
Freescale Semiconductor
Number
Page
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