MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 530

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.4.4.4.2
If BR
the LCSn for that bank with timing as specified in the UPM RAM word CST
affects only the assertion and negation of the appropriate LCSn signal. The state of the selected LCSn
signal of the corresponding bank depends on the value of each CST
control LCSn signals.
10-82
Bits
n
30
31
[MSEL] of the accessed bank selects a UPM on the currently requested cycle, the UPM manipulates
Name
TODT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LAST
Chip-Select Signal Timing (CST
UPMA/B/C
GPCM
FCM
be guaranteed between two successive accesses to the same memory bank. This feature is
critical when DRAM requires a RAS precharge time. TODT turns the timer on to prevent another
UPM access to the same bank until the timer expires.The disable timer period is determined in
M x MR[DS n ]. The disable timer does not affect memory accesses to different banks. Note that
TODT must be set together with LAST, otherwise it is ignored.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
signal timing set in the RAM word is applied to the current (and last) cycle. However, if the
disable timer is activated and the next access is to the same bank, execution of the next UPM
pattern is held off and the control signal values specified in the last word are extended in
duration for the number of clock cycles specified in M x MR[DS n ].
0 The UPM continues executing RAM words.
1 Indicates the last RAM word in the program. The service to the UPM request is done after
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to
Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
this cycle concludes.
Table 10-40. RAM Word Field Descriptions (continued)
Figure 10-65. LCS n Signal Selection
Bank Selected
BR n [MSEL]
MUX
n
)
Description
Switch
n
bit.
Figure 10-65
n
fields. The selected UPM
Freescale Semiconductor
LCS0
LCS1
LCS2
LCS3
shows how UPMs