MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 452

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.1.3.2
The eLBC provides the ID of a transaction source on external device pins. When those pins are selected,
the 5-bit internal ID of the current transaction source appears on LSRCID[0:4] whenever valid address or
data is available on the eLBC external pins. The reserved value of 0x1F, which indicates invalid address
or data, appears on the source ID pins at all other times. The combination of a valid source ID (any value
except 0x1F) and the value of external address latch enable (LALE) and data valid (LDVAL) facilitate
capturing useful debug data as follows:
The LSRCID[0:4] and LDVAL signals are multiplexed with other functions sharing the same external
pins. Refer to
learn how to enable the LSRCID/LDVAL pins.
10.2
Table 10-1
also shows the reset state of all external signals during assertion of HRESET. For more information on the
use of some of these signals as reset configuration signals on the device, see “Power on Reset Flow.”
10-4
LCS[0:3]
•
•
LGPL0/
LGPL1/
LGPL2/
LFWE/
LFCLE
LWE0/
LWE1/
LFALE
Name
LFRE
LALE
LBS0
LBS1
LOE/
If a valid source ID is detected on LSRCID[0:4] and LALE is asserted, a valid full 26-bit address
may be latched from LAD[0:15] and combined with LA[16:25].
If a valid source ID is detected on LSRCID[0:4] and LDVAL is asserted, valid data may be latched
from LAD.
External Signal Descriptions
contains a list of external signals related to the eLBC and summarizes their function. The table
Source ID Debug Mode
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Chapter 3, “Signal Descriptions,” and Chapter 4, “Reset, Clocking, and Initialization,”
Function(s)
Alternate
LGPL0
LFCLE
LGPL1
LFALE
LGPL2
LFWE
LWE0
LBS0
LFRE
LWE
LOE
LBS
—
—
Table 10-1. Signal Properties—Summary
GPCM
GPCM
GPCM
Mode
FCM
UPM
UPM
UPM
FCM
UPM
FCM
FCM
UPM
—
—
External address latch enable
Chip selects 0–3
Write enable 0
Write enable
Byte (lane) select 0
Write enable 1
Byte (lane) select 1
General purpose line 0
Flash command latch enable
General purpose line 1
Flash address latch enable
Output enable
Flash read enable
General purpose line 2
Descriptions
Signals
No. of
1
4
1
1
1
1
1
1
1
1
1
1
1
1
Freescale Semiconductor
I/O
O
O
O
O
O
O
O
Reset State
(Outputs)
Reset_cfg
Reset_cfg
Reset_cfg
Reset_cfg
Reset_cfg
Reset_cfg
to