MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 342
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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e300 Processor Core Overview
Table 7-5
7-24
Note: The clock configuration bits reflect the state of the pll_cfg[0:6] signals.
11–12
14–15
7–31
Bits
Bits
0–3
10
11
12
13
4
5
6
7
8
9
MESISTATE
Name
shows the bit definitions for HID2.
—
ELRW
Name
EBQS
NOKS
EBPX
IFEB
IFEC
HBE
LET
—
—
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved, should be cleared
Reserved, should be cleared.
True little-endian. This bit enables true little-endian mode operation for instruction and data accesses.
This bit is set to reflect the state of the tle signal at the negation of hreset . This bit is used in
conjunction with MSR[LE] to determine the endian mode of operation.
0 No function
1 True little-endian mode, when MSR[LE] = 1
Changing the value of this bit during normal operation is not recommended
Instruction fetch burst extension. This bit enables the instruction fetch burst extension.
0 Instruction fetch burst extension disabled
1 Instruction fetch burst extension enabled
Reserved, should be cleared.
MESI state enable. This bit enables the four-state MESI cache coherency protocol.
0 MESI disabled. The data cache uses a three-state MEI coherency protocol.
1 MESI enabled. The data cache uses a four-state MESI protocol.
Instruction fetch cancel extension. This bit enables the instruction fetch cancel extension.
0 Instruction fetch cancel extension disabled
1 Instruction fetch cancel extension enabled
Enable BIU queue sharing. This bit enables data cache queue sharing.
0 Data cache queue sharing disabled
1 Data cache queue sharing enabled
Enable BIU pipeline extension.This bit enables the bus interface unit pipeline extension.
0 BIU pipeline extension disabled; 1 level pipeline
1 BIU pipeline extension enabled; 1-1/2 level pipeline
Reserved for e300c1, should be cleared.
Enable weighted LRU. This bit enables the use of an adjusted (weighted) LRU.
0 Normal operation.
1 The dcbt, dcbtst, and dcbz instructions use and adjusted (weighted) LRU such that they always
No kill for snoop. This bit enables the forcing of kill-type snoops to flush data instead of killing it.
0 Normal operation.
1 Forces write-with-kill snoops to flush instead of kill (snoop can never kill data).
High BAT enable. Regardless of the setting of HID2[HBE], these BATs are accessible by mfspr and
mtspr.
0 IBAT[4–7] and DBAT[4–7] are disabled
1 IBAT[4–7] and DBAT[4–7] are enabled
Reserved, should be cleared.
select and replace the lowest unlocked way in the data cache.
Table 7-4. HID1 Bit Descriptions (continued)
Table 7-5. e300HID2 Bit Descriptions
Description
Description
Freescale Semiconductor
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