MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 762
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Three-Speed Ethernet Controllers
TR03WT has no effect. A description of how queue weights affect eTSEC’s round-robin algorithm
appears in
describes the TR03WT register.
Table 15-20
15.5.3.2.7
When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register
determines the weighting applied to each enabled transmit queue for queues 4 to 7. For priority-based
scheduling, TR47WT has no effect. A description of how queue weights affect eTSEC’s modified
weighted round-robin algorithm appears in
Queuing (MWRR).” Figure 15-16
15-44
16–23 WT2 Weighting value for TxBD ring 2 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
24–31 WT3 Weighting value for TxBD ring 3 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
Offset eTSEC1:0x2_4144; eTSEC2:0x2_5144
Reset
8–15
Bits Name
0–7
Offset eTSEC1:0x2_4140; eTSEC2:0x2_5140
Reset
W
R
W
R
WT0 Weighting value for TxBD ring 0 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
WT1 Weighting value for TxBD ring 1 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
0
0
Section 15.6.4.3.2, “Modified Weighted Round-Robin Queuing (MWRR).” Figure 15-15
of WT0 × 64 bytes of data are scheduled for transmission from TxBD ring 0. Clearing this field prevents
transmission.
of WT1 × 64 bytes of data are scheduled for transmission from TxBD ring 1. Clearing this field prevents
transmission.
of WT2 × 64 bytes of data are scheduled for transmission from TxBD ring 2. Clearing this field prevents
transmission.
of WT3 × 64 bytes of data are scheduled for transmission from TxBD ring 3. Clearing this field prevents
transmission.
describes the fields of the TR03WT register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
TxBD Ring 4–7 Weighting Register (TR47WT)
WT4
WT0
7
7
8
Figure 15-15. TR03WT Register Definition
Figure 15-16. TR47WT Register Definition
Table 15-20. TR03WT Field Descriptions
8
describes the definition for the TR47WT register.
WT5
WT1
Section 15.6.4.3.2, “Modified Weighted Round-Robin
All zeros
All zeros
15 16
Description
15 16
WT6
WT2
23 24
23 24
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
WT7
WT3
31
31
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