MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 246

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface (S08SPI16V1)
15.1.2
The SPI includes these distinctive features:
15.1.3
The SPI functions in three modes, run, wait, and stop.
The SPI is completely disabled in all other stop modes. When the CPU wakes from these stop modes, all
SPI register content will be reset.
This is a high level description only, detailed descriptions of operating modes are contained in section
Section 15.4.9, “Low Power Mode
15.1.4
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
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Master mode or slave mode operation
Full-duplex or single-wire bidirectional mode
Programmable transmit bit rate
Double-buffered transmit and receive data register
Serial clock phase and polarity options
Slave select output
Mode fault error flag with CPU interrupt capability
Control of SPI operation during wait mode
Selectable MSB-first or LSB-first shifting
Programmable 8- or 16-bit data transmission length
Receive data buffer hardware match feature
Run Mode
This is the basic mode of operation.
Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPIxC2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop Mode
The SPI is inactive in stop3 mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after the CPU goes into Run Mode. If
the SPI is configured as a slave, reception and transmission of a data continues, so that the slave
stays synchronized to the master.
Features
Modes of Operation
Block Diagrams
MC9S08JM60 Series Data Sheet, Rev. 3
Options.”
Freescale Semiconductor