MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 310

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Device Controller (S08USBV1)
17.3.13 Endpoint Control Register (EPCTLn, n=0-6)
The endpoint control registers contains the endpoint control bits (EPCTLDIS, EPRXEN, EPTXEN, and
EPHSHK) for each endpoint available within the USB module for a decoded address. These four bits
define all of the control necessary for any one endpoint. The formats for these registers are shown in the
tables below. Endpoint 0 (ENDP0) is associated with control pipe 0 which is required by the USB for all
functions. Therefore, after a USBRST interrupt has been received, the microcontroller must set EPCTL0
to contain 0x0D.
310
(EP0-6)
FRM[10:8]
Reset
Reset
EPCTLDIS
Field
EPRXEN
EPTXEN
2–0
W
R
Field
W
R
4
3
2
Frame Number — These bits represent the high order bits of the 11-bit frame number.
0
0
7
0
0
7
Endpoint Control — This bit defines if an endpoint is enabled and the direction of the endpoint. The
endpoint enable/direction control is defined in
Endpoint Rx Enable — This bit defines if an endpoint is enabled for OUT transfers. The endpoint
enable/direction control is defined in
Endpoint Tx Enable — This bit defines if an endpoint is enabled for IN transfers. The endpoint
enable/direction control is defined in
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 17-16. Frame Number Register High (FRMNUMH)
0
0
6
0
0
6
Figure 17-17. Endpoint Control Register (EPCTLn)
Table 17-17. FRMNUMH Field Descriptions
Table 17-18. EPCTLn Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
0
0
5
0
0
5
EPCTLDIS
Table
Table
0
4
0
0
4
17-19.
17-19.
Description
Table
Description
EPRXEN
17-19.
3
0
3
0
0
EPTXEN
FRM10
0
0
2
2
EPSTALL
Freescale Semiconductor
FRM9
0
0
1
1
EPHSHK
FRM8
0
0
0
0