MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 91

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
PTDPE[7:0]
PTDSE[7:0]
PTDDS[7:0]
Reset
Reset
Reset
Field
Field
Field
7:0
7:0
7:0
W
W
W
R
R
R
PTDPE7
PTDSE7
PTDDS7
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
output drive for the associated PTD pin.
0 Low output drive enabled for port D bit n.
1 High output drive enabled for port D bit n.
0
1
0
7
7
7
Figure 6-20. Output Slew Rate Control Enable for Port D (PTDSE)
Figure 6-21. Output Drive Strength Selection for Port D (PTDDS)
PTDDS6
PTDPE6
PTDSE6
0
1
0
6
6
6
Figure 6-19. Internal Pullup Enable for Port D (PTDPE)
Table 6-20. PTDDS Register Field Descriptions
Table 6-18. PTDPE Register Field Descriptions
Table 6-19. PTDSE Register Field Descriptions
PTDDS5
PTDPE5
PTDSE5
MC9S08JM60 Series Data Sheet, Rev. 3
0
1
0
5
5
5
PTDDS4
PTDPE4
PTDSE4
0
1
0
4
4
4
Description
Description
Description
PTDPE3
PTDSE3
PTDDS3
3
0
3
1
3
0
PTDPE2
PTDSE2
PTDDS2
0
1
0
2
2
2
Chapter 6 Parallel Input/Output
PTDPE1
PTDSE1
PTDDS1
0
1
0
1
1
1
PTDDS0
PTDPE0
PTDSE0
0
1
0
0
0
0
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