MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 308

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Device Controller (S08USBV1)
17.3.10 Control Register (CTL)
The CTL provides various control and configuration information for the USB module.
308
TSUSPEND
CRESUME
Reset
Field
ODDRST
ODD
USBEN
IN
3
2
Field
W
R
5
2
1
0
In/Out Transaction — This bit indicates whether the last BDT updated was for a transmit (IN) transfer or a
receive (OUT) data transfer.
0 Last transaction was a receive (OUT) data transfer
1 Last BDT updated was for transmit (IN) transfer
Odd/Even Transaction —This bit indicates whether the last buffer descriptor updated was in the odd bank of
the BDT or the even bank of the BDT, See earlier section for more information on BDT address generation.
0 Last buffer descriptor updated was in the EVEN bank
1 Last buffer descriptor updated was in the ODD bank
0
7
Transaction Suspend — This bit is set by the serial interface engine (SIE) when a setup token is received,
allowing software to dequeue any pending packet transactions in the BDT before resuming token processing.
The TSUSPEND bit informs the processor that the SIE has disabled packet transmission and reception.
Clearing this bit allows the SIE to continue token processing.
0 Allows the SIE to continue token processing
1 Set by the SIE when a setup token is received; SIE has disabled packet transmission and reception.
Resume Signaling — Setting this bit will allow the USB module to execute resume signaling. This will allow
the USB module to perform remote wakeup. Software must set CRESUME to 1 for the amount of time
required by the USB Specification Rev. 2.0 and then clear it to 0.
0 Do not execute remote wakeup
1 Execute resume signaling - remote wakeup
Odd Reset — Setting this bit will reset all the buffer descriptor ODD ping-pong bits to 0 which will then specify
the EVEN descriptor bank. This bit is used with double-buffered endpoints 5 and 6. This bit has no effect on
endpoints 0 through 4.
0 Do not reset
1 Reset all the buffer descriptor ODD ping/pong bits to 0 which will then specify the EVEN descriptor bank
USB Enable Setting this bit will enable the USB module to operate. Setting this bit causes the SIE to reset
all of its ODD bits to the BDTs. Thus, setting this bit will reset much of the logic in the SIE.
0 Disable the USB module
1 Enable the USB module for operation, will not affect Transceiver and VREG.
0
6
Table 17-13. STAT Field Descriptions (continued)
TSUSPEND
Figure 17-13. Control Register (CTL)
Table 17-14. CTL Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
0
5
0
4
Description
Description
3
0
CRESUME
0
2
ODDRST
Freescale Semiconductor
0
1
USBEN
0
0