MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 322

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Device Controller (S08USBV1)
17.4.4.3
The USB includes a number of error checking and recovery mechanisms to ensure reliable data transfer.
One such exception occurs when the host sends a SETUP packet to a device, and the host never receives
the acknowledge handshake from the device. In this case, the host will retry the SETUP packet.
Endpoint 0 request handlers on the device must be aware of the possibility that after receiving a correct
SETUP packet, they could receive another SETUP packet before the data phase actually begins.
17.4.5
The USB host allocates time in 1.0 ms chunks called “Frames” for the purposes of packet scheduling. The
USB host starts each frame with a broadcast token called SOF (start of frame) that includes an 11-bit
sequence number. The TOKSOF interrupt is used to notify firmware when an SOF token was received.
Firmware can read the current frame number from the FRMNUML/FRMNUMH registers.
In general, the SOF interrupt is only monitored by devices using isochronous endpoints to help ensure that
the device and host remain synchronized.
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2. Create BDT entries for Endpoint 0 OUT, and set the DTS and OWN bits to 1.
3. Wait for interrupt TOKDNE.
4. Read STAT register.
5. Read Endpoint 0 OUT BD.
6. Decode and process the setup packet.
7. After processing the data phase (if there was one), create a zero-byte status phase transaction.
— The status register must show Endpoint 0, RX. If it does not, then assert the EPSTALL bit in
— Verify that the token type is a SETUP token. If it is not, then assert the EPSTALL bit in the
— If the direction field in the setup packet indicates an OUT transfer, then process the out data
— If the direction field in the setup packet indicates an IN transfer, then process the in data phase
— This is accomplished for an OUT data phase (IN status phase) by setting the BC to 0 in the next
— Firmware can verify completion of the data phase by verifying the received token in the BD on
the endpoint control register.
endpoint control register.
phase to receive exactly the number of bytes specified in the wLength field of the setup packet.
to deliver no more than the number of bytes specified in the wLength field. Note that it is
common for the host to request more bytes than it needs, expecting the device to only send as
much as it needs to.
BD, while also setting OWN=1. For an IN data phase (OUT status phase), the host will send a
zero-byte packet to the device.
receipt of the TOKDNE interrupt. If the data phase was of type IN, then the status phase token
will be OUT. If the data phase was of type OUT, then the status phase token will be IN.
Start of Frame Processing
Endpoint 0 Exception Conditions
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor