MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 61

IC MCU 8BIT 32K FLASH 44-LQFP

MC9S08JM32CLD

Manufacturer Part Number
MC9S08JM32CLD
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08JM32CLD

Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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0
1
SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of flash.
4.7.3
Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
4.7.4
During reset, the contents of the nonvolatile location NVPROT is copied from flash into FPROT. This
register may be read at any time, but user program writes have no meaning or effect. Background debug
commands can write to FPROT.
Freescale Semiconductor
Background commands can be used to change the contents of these bits in FPROT.
KEYACC
Reset
Reset
Field
5
W
W
R
R
FPS7
Flash Configuration Register (FCNFG)
Flash Protection Register (FPROT and NVPROT)
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
(1)
0
0
7
7
= Unimplemented or Reserved
FPS6
(1)
0
0
6
6
This register is loaded from nonvolatile location NVPROT during reset.
Figure 4-7. Flash Configuration Register (FCNFG)
SEC01:SEC00
Table 4-10. FCNFG Register Field Descriptions
Figure 4-8. Flash Protection Register (FPROT)
0:0
0:1
1:0
1:1
KEYACC
MC9S08JM60 Series Data Sheet, Rev. 3
FPS5
(1)
0
5
5
Table 4-9. Security States
FPS4
(1)
0
0
4
4
Description
Section 4.6,
FPS3
(1)
3
0
0
3
Description
unsecured
secure
secure
secure
“Security.”
FPS2
(1)
0
0
2
2
FPS1
(1)
0
0
1
1
Chapter 4 Memory
FPDIS
(1)
0
0
0
0
61

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