MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 366

IC MCU 8BIT 32K FLASH 44-LQFP

MC9S08JM32CLD

Manufacturer Part Number
MC9S08JM32CLD
Description
IC MCU 8BIT 32K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08JM32CLD

Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08JM32CLD
Manufacturer:
Freescale Semiconductor
Quantity:
1 948
Part Number:
MC9S08JM32CLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S08JM32CLD
0
Appendix A Electrical Characteristics
A.12.3
Table A-15
366
Num
10
11
12
and
SPI Characteristics
1
2
3
4
5
6
7
8
9
1
Figure A-10
C
D
D
D
D
D
D
D
D
D
D
D
D
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time Master and
Slave
Clock (SPSCK) low time Master and
Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
TPMxCHn
TPMxCHn
through
Characteristic
Table A-15. SPI Electrical Characteristic
Figure A-9. Timer Input Capture Pulse
MC9S08JM60 Series Data Sheet, Rev. 3
Figure A-13
3
4
2
Master
Master
Master
Master
Master
Master
Master
Master
describe the timing requirements for the SPI system.
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
t
t
ICPW
ICPW
Symbol
t
t
t
t
t
t
t
t
t
t
SCKH
SCKL
HI(M)
t
t
SI(M)
HI(S)
Lead
Lead
SI(S)
t
t
t
t
SCK
SCK
t
f
f
Lag
Lag
HO
HO
t
SO
SO
op
op
dis
A
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
1/2
1/2
30
30
30
30
25
25
dc
/2048
2
4
0
– 25
– 25
f
f
2048
Max
Bus
Bus
1/2
1/2
40
40
Freescale Semiconductor
/2
/4
Unit
t
t
t
t
t
t
SCK
SCK
SCK
SCK
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc

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