MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 76

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Chapter 5 Resets, Interrupts, and System Configuration
5.7.5
5.7.6
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
76
COPCLKS
This bit can be written only one time after reset. Additional writes are ignored.
Reset
Reset
SPI1FE
SPI2FE
COPW
Field
ACIC
7
6
2
1
0
W
W
R
R
COPCLKS
System Options Register 2 (SOPT2)
System Device Identification Register (SDIDH, SDIDL)
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz LPO clock is source to COP.
1 Bus clock is source to COP.
COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.
SPI1 Ports Input Filter Enable
0 Disable input filter on SPI1 port pins to allow for higher maximum SPI baud rate.
1 Enable input filter on SPI1 port pins to eliminate noise and restrict maximum SPI baud rate.
SPI2 Ports Input Filter Enable
0 Disable input filter on SPI2 port pins to allow for higher maximum SPI baud rate.
1 Enable input filter on SPI2 port pins to eliminate noise and restrict maximum SPI baud rate.
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM input channel 0.
0 ACMP output not connected to TPM input channel 0.
1 ACMP output connected to TPM input channel 0.
—
0
7
7
1
Figure 5-7. System Device Identification Register — High (SDIDH)
= Unimplemented or Reserved
= Unimplemented or Reserved
COPW
—
0
6
6
1
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
—
0
0
5
5
—
0
0
4
4
Description
ID11
3
0
0
3
0
SPI1FE
ID10
1
0
2
2
Freescale Semiconductor
SPI2FE
ID9
1
0
1
1
ACIC
ID8
0
0
0
0