MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 69

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pullup
or pull-down depending on the polarity chosen. If the user desires to use an external pullup or pull-down,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
5.5.2.2
The IRQMOD control bit re-configure the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3
Table 5-1
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Freescale Semiconductor
Number
31 to 30
Vector
29
28
27
26
25
24
provides a summary of all interrupt sources. Higher-priority sources are located toward the
Interrupt Vectors, Sources, and Local Masks
Edge and Level Sensitivity
0xFFCC:FFCD
0xFFCA:FFCB
0xFFCE:FFCF
0xFFC0:FFC1
0xFFC2:FFC3
0xFFC4:FFC5
0xFFC6:FFC7
0xFFC8:FFC9
This pin does not contain a clamp diode to V
above V
be as low as V
all the way to V
(High/Low)
Address
Table 5-1. Vector Summary (from Lowest to Highest Priority)
DD
. The voltage measured on the internally pulled up IRQ pin may
DD
Vector Name
Vkeyboard
DD
Vsci2tx
Vacmp
– 0.7 V. The internal gates connected to this pin are pulled
Vadc
Vrtc
Viic
.
MC9S08JM60 Series Data Sheet, Rev. 3
Module
System
control
ACMP
Unused vector space (available for user program)
SCI2
ADC
KBI
IIC
NOTE
Source
COCO
TDRE
RTIF
IICIF
ACF
KBF
TC
DD
Chapter 5 Resets, Interrupts, and System Configuration
and must not be driven
Enable
AIEN
RTIE
IICIE
ACIE
KBIE
TCIE
TIE
RTC real-time interrupt
Keyboard pins
SCI2 transmit
Description
ACMP
ADC
IIC
69