MC9S08JM32CLD Freescale Semiconductor, MC9S08JM32CLD Datasheet - Page 247

• Manufacturer Part Number: MC9S08JM32CLD
• Description: IC MCU 8BIT 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM32CLD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.1.4.1
Figure 15-3
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
15.1.4.2
Figure 15-4
Data is written to the double-buffered transmitter (write to SPIxDH:SPIxDL) and gets transferred to the
SPI shift register at the start of a data transfer. After shifting in 8 or 16 bits (as determined by SPIMODE
bit) of data, the data is transferred into the double-buffered receiver where it can be read (read from
SPIxDH:SPIxDL). Pin multiplexing logic controls connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
Freescale Semiconductor
is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
SPI System Block Diagram
SPI Module Block Diagram
GENERATOR
SPI SHIFTER
8 OR 16 BITS
MASTER
CLOCK
Figure 15-3. SPI System Connections
MC9S08JM60 Series Data Sheet, Rev. 3
MOSI
MISO
SPSCK
SS
SPSCK
MOSI
MISO
SS
SLAVE
Serial Peripheral Interface (S08SPI16V1)
SPI SHIFTER
8 OR 16 BITS
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