MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 102

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 2 64 Kbyte Flash Module (S12FTS64KV3)
2.6.2
The MCU can be unsecured in special single-chip mode by erasing the Flash module by the following
method :
After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special
single-chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the
UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security
state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state by the following method:
2.7
2.7.1
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash memory according to
2.7.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector / block being erased is not guaranteed.
2.8
The Flash module can generate an interrupt when all Flash command operations have completed, when the
Flash address, data, and command buffers are empty.
102
Flash address, data and command buffers empty
All Flash commands completed
•
•
•
•
•
Reset the MCU into special single-chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass
erase command write sequence to erase the Flash memory.
Send BDM commands to execute a word program sequence to program the Flash security byte to
the unsecured state and reset the MCU.
FPROT — Flash Protection Register (see
FCTL — Flash Control Register (see
FSEC — Flash Security Register (see
Resets
Interrupts
Unsecuring the Flash Module in Special Single-Chip Mode using
BDM
Flash Reset Sequence
Reset While Flash Command Active
Interrupt Source
Table 2-19. Flash Interrupt Sources
MC9S12NE64 Data Sheet, Rev. 1.1
CBEIF (FSTAT register) CBEIE (FCNFG register)
CCIF (FSTAT register)
Section
Section
Table
Interrupt Flag
Section
2-1:
2.3.2.9).
2.3.2.2).
2.3.2.5).
CCIE (FCNFG register)
Local Enable
Freescale Semiconductor
Global (CCR) Mask
I Bit
I Bit