MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 479

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.3.2.3
Freescale Semiconductor
Reset
Reset
Field
15:0
W
W
R
R
Bit 15
Bit 7
Trace Buffer Data Bits — The trace buffer data bits contain the data of the trace buffer. This register can be read
only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the
trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the
debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same
capture mode bit settings as when the trace buffer data was recorded (See
Trace
Debug Trace Buffer Register (DBGTB)
15
u
u
7
Buffer”). Because reads will reflect the contents of the trace buffer RAM, the reset state is undefined.
= Unimplemented or Reserved
= Unimplemented or Reserved
Bit 14
Figure 18-6. Debug Trace Buffer Register High (DBGTBH)
Bit 6
Figure 18-7. Debug Trace Buffer Register Low (DBGTBL)
14
u
u
6
Table 18-7. DBGTB Field Descriptions
Bit 13
Bit 5
MC9S12NE64 Data Sheet, Rev. 1.1
13
u
u
5
Bit 12
Bit 4
12
u
u
4
Description
Bit 11
Bit 3
11
u
u
3
Bit 10
Bit 2
Section 18.4.2.9, “Reading Data from
10
u
u
2
Memory Map and Register Definition
Bit 9
Bit 1
u
u
9
1
Bit 8
Bit 0
u
u
8
0
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