MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 326

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.3.2.15 Ethernet Buffer Configuration (BUFCFG)
Module Base + $18
Read: Anytime.
Write: See each field description.
BUFMAP — Buffer Size and Starting Address Mapping
MAXFL — Receive Maximum Frame Length
326
RESET:
W
This 3-bit field can be written once after a hardware or software reset and only while EMACE is clear.
Any write to this field while EMACE is set is ignored.
This field specifies the buffer size and the base address within system RAM for the receive and
transmit Ethernet buffers.
starting address of the system RAM depends on its position within the on-chip system memory map.
This 11-bit field can be written anytime, but the user must not change this field while EMACE is set.
The 11-bit field specifies the maximum receive frame length in bytes. Receive frames exceeding
MAXFL causes the BREIF event bit to set and an interrupt occurs if the BREIE is also set. Written
values equal-to or less-than 0x040 (64 decimal) use the minimum of 0x040. Written values equal-to
or greater-than 0x5EE (1518 decimal) use the maximum of 0x5EE.
R
BUFMAP
5 – 7
15
0
1
2
3
4
0
0
= Unimplemented or Reserved
14
1
Address
Starting
System
0x0000
0x0000
0x0000
0x0000
0x0000
BUFMAP
RAM
13
0
Table 11-7. Buffer Mapping Configuration on System RAM
Figure 11-16. Ethernet Buffer Configuration (BUFCFG)
12
0
RX Buffer A
Table 11-7
(Bytes)
Size
1.5K
128
256
512
1K
11
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
10
0x0000 - 0x00FF
0x0000 - 0x01FF
0x0000 - 0x03FF
0x0000 - 0x05FF
1
shows the mapping configuration for the system RAM. The
0x0000 - 0x007F
RX Buffer A
Address
Space
9
0
8
1
Reserved
RX Buffer
(Bytes)
B size
7
1
1.5K
128
256
512
1K
6
1
0x0600 - 0x0BFF
0x0080 - 0x00FF
0x0100 - 0x01FF
0x0200 - 0x03FF
0x0400 - 0x07FF
MAXFL
RX Buffer B
Address
5
1
Space
4
0
3
1
Freescale Semiconductor
TX Buffer Start
Address
0x0C00
0x0100
0x0200
0x0400
0x0800
2
1
1
1
0
0