MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 499

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.4.3.2
A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a
successful comparator C match can be accomplished regardless of the mode of operation for comparator
A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or
forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1
mode.
18.5
The DBG module is disabled after reset.
The DBG module cannot cause a MCU reset.
18.6
The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an
SWI interrupt will be generated.
Freescale Semiconductor
BEGIN
Resets
Interrupts
0
0
0
0
1
1
1
1
Breakpoint Based on Comparator C
Because breakpoints cannot be disabled when the DBG is armed, one must
be careful to avoid an “infinite breakpoint loop” when using tagged-type C
breakpoints while the DBG is armed. If BDM breakpoints are selected,
executing a TRACE1 instruction before the GO instruction is the
recommended way to avoid re-triggering a breakpoint if one does not wish
to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in
the SWI interrupt service routine is the recommended way to avoid
re-triggering a breakpoint.
TRGSEL
0
0
1
1
0
0
1
1
DBGBRK
MC9S12NE64 Data Sheet, Rev. 1.1
Table 18-26. Breakpoint Setup
0
1
0
1
0
1
0
1
Fill trace buffer until trigger address
(no CPU breakpoint — keep running)
Fill trace buffer until trigger address, then a forced breakpoint
request occurs
Fill trace buffer until trigger opcode is about to execute
(no CPU breakpoint — keep running)
Fill trace buffer until trigger opcode about to execute, then a
tagged breakpoint request occurs
Start trace buffer at trigger address
(no CPU breakpoint — keep running)
Start trace buffer at trigger address, a forced breakpoint
request occurs when trace buffer is full
Start trace buffer at trigger opcode
(no CPU breakpoint — keep running)
Start trace buffer at trigger opcode, a forced breakpoint request
occurs when trace buffer is full
NOTE
Type of Debug Run
Resets
499