MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 364

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.3.4
PHY also contains a number of registers to set its internal mode of operation. These registers can be set
through the external management interface to determine capabilities such as speed, test-mode, circuit
bypass mode, interrupt setting, etc. The PHY register set includes registers 16 through 29. These registers
are not part of the MCU memory map.
12.3.4.1 Interrupt Control Register
MII Register Address 16 (%10000)
Read: Anytime
Write: Anytime
ACKIE — Acknowledge Bit Received Interrupt Enable
PRIE — Page Received INT Enable
LCIE — Link Changed Enable
ANIE — Auto-Negotiation Changed Enable
PDFIE — Parallel Detect Fault Enable
RFIE — Remote Fault Interrupt Enable
JABIE — Jabber Interrupt Enable
364
RESET:
W
R
1 = Enable interrupt when the acknowledge bit is received from the link partner
0 = Disable interrupt when acknowledge bit is received
1 = Enable interrupt when a new page is received
0 = Disable interrupt when a page is received
1 = Enable interrupt when the link status changes
0 = Disable interrupt when the link status changes
1 = Enable interrupt when the state of the auto-negotiation state machine has changed since the last
0 = Disable interrupt when the state of the auto-negotiation state machine has changed since the last
1 = Enable interrupt on a parallel detect fault
0 = Disable interrupt on a parallel detect fault
1 = Enable interrupt on a parallel detect fault
0 = Disable interrupt on a parallel detect fault
1 = Enable setting interrupt on detection of a jabber condition
0 = Disable setting interrupt on detection of a jabber condition
15
PHY-Specific Registers
access of this register
access of this register
0
0
= Unimplemented or Reserved
ACKIE
14
0
PRIE
13
0
LCIE
12
0
Figure 12-15. Interrupt Control Register
ANIE
11
0
MC9S12NE64 Data Sheet, Rev. 1.1
PDFIE
10
0
RFIE
9
0
JABIE
8
0
7
0
0
ACKR
6
0
PGR
5
0
LKC
4
0
ANC
3
0
Freescale Semiconductor
PDF
2
0
RMTF
1
0
JABI
0
0