MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 123

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

PIFG[7:0] — Interrupt Flags Port G
3.3.2.4
3.3.2.4.1
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The EMAC MII external interface takes precedence over general-purpose I/O function if the EMAC
module is enabled in external PHY mode. If the EMAC MII external interface is enabled PH[6:0] pins
become MII_TXER, MII_TXEN, MII_TXCLK, MII_TXD[3:0]. Please refer to the EMAC block
description chapter for details.
3.3.2.4.2
Read:Anytime.
Write:Never, writes to this register have no effect.
Freescale Semiconductor
Module Base + $18
1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable
0 = No active edge pending.
EMAC
Reset:
Read:
Write:
Module Base + $19
KWU
Reset:
Read:
Write:
bit is set).
Writing a “1” clears the associated flag.
Writing a “0” has no effect.
Port H Registers
I/O Register (PTH)
Input Register (PTIH)
Bit 7
—
0
Bit 7
—
0
MII_TXER MII_TXEN MII_TXCLK MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0
= Reserved or unimplemented
= Reserved or unimplemented
PTH6
PTIH6
6
0
—
6
Figure 3-24. Port H Input Register (PTIH)
Figure 3-23. Port H I/O Register (PTH)
PTH5
MC9S12NE64 Data Sheet, Rev. 1.1
PTIH5
5
0
—
5
PTH4
PTIH4
—
4
0
4
PTIH3
KWH
PTH3
—
3
3
0
PTIH2
PTH2
—
2
2
0
Memory Map and Register Descriptions
PTIH1
PTH1
—
1
1
0
PTIH0
Bit 0
PTH0
—
Bit 0
0
123