MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 217

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

7.3.2.5
This register selects the conversion clock frequency, the length of the second phase of the sample time and
the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
SMP[1:0]
PRS[4:0]
Reset
SRES8
Field
6–5
4–0
W
7
R
SRES8
ATD Control Register 4 (ATDCTL4)
0
7
A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The
A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
0 10-bit resolution
Sample Time Select — These two bits select the length of the second phase of the sample time in units of
ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler
value (bits PRS4–0). The sample time consists of two phases. The first phase is two ATD conversion clock
cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node.
The second phase attaches the external analog signal directly to the storage node for final charging and high
accuracy.
ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
frequency is calculated as follows:
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler
ATDclock
8-bit resolution
value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.
Table 7-12
SMP1
Table 7-11
0
0
1
1
SMP1
=
[
-------------------------------- -
0
6
BusClock
[
PRS
illustrates the divide-by operation and the appropriate range of the bus clock.
Figure 7-7. ATD Control Register 4 (ATDCTL4)
+
lists the lengths available for the second sample phase.
1
Table 7-10. ATDCTL4 Field Descriptions
]
]
×
SMP0
SMP0
0.5
Table 7-11. Sample Time Select
MC9S12NE64 Data Sheet, Rev. 1.1
0
1
0
1
0
5
PRS4
0
4
Length of 2nd Phase of Sample Time
16 A/D conversion clock periods
Description
2 A/D conversion clock periods
4 A/D conversion clock periods
8 A/D conversion clock periods
PRS3
0
3
PRS2
1
2
Memory Map and Register Definition
PRS1
0
1
PRS0
1
0
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