MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 381

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

13.2 Signal Description
13.2.1 Overview
Due to the nature of VREG_PHY being a voltage regulator providing the chip internal power
supply voltages most signals are power supply signals connected to pads.
13.2.2 Detailed Signal Descriptions
Check device level specification for connectivity of the signals.
13.2.2.1 VDDR,VDDRAUX1,2,3, VSS - Regulator Power Inputs
Signal VDDR/VDDRAUX1,2,3 are the power inputs of VREG_PHY. All currents sourced into
the regulator loads flow through these pins. A chip external decoupling capacitor (100nF...220nF,
X7R ceramic) between VDDR/VDDRAUX1,2,3 and VSS can smoothen ripple on
VDDR/VDDRAUX1,2,3.
If the regulator shall be bypassed, VDDR should be tied to ground. In Shutdown Mode pin VDDR
should also be tied to ground on devices without VREGEN pin.
Freescale Semiconductor
Table 13-1 shows all signals of VREG_PHY associated with pins.
VREGEN (optional)
VDDRAUX1
VDDRAUX2
VDDRAUX3
VDDAUX1
VDDAUX2
VDDAUX3
VSSAUX1
VSSAUX2
VSSAUX3
VDDPLL
VSSPLL
VDDR
Name
VDDA
VSSA
VDD
VSS
Port
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Table 13-1. VREG_PHY - Signal Properties
VREG_PHY secondary output (positive supply)
VREG_PHY primary output (positive supply)
VREG_PHY fourth output (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY power input (positive supply)
VREG_PHY third output (positive supply)
VREG_PHY (Optional) Regulator Enable
VREG_PHY fifth output (positive supply)
MC9S12NE64 Data Sheet, Rev. 1.1
VREG_PHY quiet input (positive supply)
VREG_PHY secondary output (ground)
VREG_PHY primary output (ground)
VREG_PHY fourth output (ground)
VREG_PHY third output (ground)
VREG_PHY fifth output (ground)
VREG_PHY quiet input (ground)
Function
Reset State
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Signal Description
Pull up
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