MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 313

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.1 Network Control (NETCTL)
Read: Anytime.
Write: See each bit description.
EMACE — EMAC Enable
ESWAI — EMAC Disabled during Wait Mode
EXTPHY — External PHY
Freescale Semiconductor
This bit can be written anytime, but the user must not modify this bit while TXACT is set.
While this bit is set, the EMAC is enabled, and reception and transmission are possible. When this bit
is cleared, the EMAC receiver and transmitter are immediately disabled, any receive in progress is
dropped, and any PAUSE timeout is cleared. EMACE has no effect on the MII management functions.
This bit can be written anytime.
When this bit is set, the EMAC receiver, transmitter, and MII management logic are disabled during
wait mode, any receive in progress is dropped, and any PAUSE timeout is cleared. The user must not
enter wait mode with the ESWAI bit set if TXACT or BUSY are asserted. While the ESWAI bit is
clear, the EMAC continues to operate during wait mode.
This bit can be written once after a hardware or software reset, but the user must not modify this bit
while EMACE or BUSY is set. While this bit is set, the EMAC is configured for an external PHY, all
the EMAC MII I/O pins are available externally, and the MII to the internal PHY is not available.
1 = Enables EMAC.
0 = Disables EMAC.
1 = EMAC is disabled during wait mode.
0 = EMAC continues to operate normally during wait mode.
Module Base + $0
RESET:
W
R
When configuring for loopback mode or for an external PHY, the user must
set the MLB or EXTPHY bit before enabling the EMAC by setting
EMACE. That is, when setting MLB or EXTPHY, the initial write to this
register should not also set the EMACE bit; separate writes must be
performed.
When configuring MLB and EXTPHY bits, any internal or external PHY
connected should be disabled to protect against possible glitches generated
on MII signals as port configuration logic settles.
EMACE
7
0
= Unimplemented or Reserved
6
0
0
Figure 11-2. Network Control (NETCTL)
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
0
ESWAI
NOTE
NOTE
4
0
EXTPHY
3
0
MLB
2
0
Memory Map and Register Descriptions
FDX
1
0
0
0
0
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