MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 367

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

FEFLTD — Far End Fault Disable
MIILBO — MII Loopback Disable
JBDE — Jabber Detect Enable (10BASE-T)
LNKTSTD — Link Test Disable (10BASE-T)
POLCORD — Disable Polarity Correction (10BASE-T)
ALGD — Disable Alignment
ENCBYP — Encoder Bypass
SCRBYP — Scrambler Bypass Mode (100BASE-TX)
TRDANALB — Transmit and Receive Disconnect and Analog Loopback
TRTST — Transmit and Receive Test (100BASE-TX)
12.4
The EPHY is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The EPHY can be configured
to support 10BASE-T or 100BASE-TX applications. The EPHY is configurable via internal registers
which are accessible through the MII management interface as well as limited configurability using the
EPHY register map.
There are five basic modes of operation for the EPHY:
Freescale Semiconductor
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1 = Far end fault detect is disabled
0 = Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation
1 = Disable MII loopback
0 = MII transmit data is looped back to the MII receive pins
1 = Enable jabber detection
0 = Disable jabber detection
1 = Disable 10BASE-T link integrity test
0 = 10BASE-T link integrity test enabled
1 = 10BASE-T receive polarity correction is disabled
0 = 10BASE-T receive polarity is automatically corrected
1 = Un-aligned mode. Available only in symbol mode
0 = Aligned mode
1 = Symbol mode and bypass 4B/5B encoder and decoder
0 = Normal mode
1 = Bypass the scrambler and de-scrambler
0 = Normal
1 = High-impedance twisted pair transmitter. Analog loopback mode overrides and forces this bit
0 = Normal operation
1 = Transmit and receive data regardless of link status
0 = Normal operation
Power down/initialization
Auto-negotiate
Functional Description
is disabled
MC9S12NE64 Data Sheet, Rev. 1.1
Functional Description
367