MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 139

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

3.6
Port G, H, and J generate a separate edge sensitive interrupt if enabled.
3.6.1
3.6.2
The PIM_9NE64 can generate wake-up interrupts from stop on port G, H, and J. For other sources of
external interrupts please refer to the respective block description chapter.
Freescale Semiconductor
Interrupts
Interrupt Sources
Recovery from Stop
BKGD pin
Vector addresses and their relative interrupt priority are determined at the
MCU level.
J[7:6]
J[3:0]
Port
G
S
H
A
B
E
K
T
L
Interrupt Source
Port G
Port H
Direction
Port J
Table 3-6. Port Integration Module Interrupt Sources
Data
input
input
input
input
input
input
input
Refer to the MEBI block description chapter for details.
Refer to the BDM block description chapter for details.
Table 3-5. Port Reset State Summary
MC9S12NE64 Data Sheet, Rev. 1.1
Pull Mode
pull-up
pull-up
pull-up
hiz
hiz
hiz
hiz
PIFJ[7:6],[3:0]
PIFG[7:0]
PIFH[6:0]
Interrupt
Flag
NOTE
Red. Drive
disabled
disabled
disabled
disabled
disabled
disabled
disabled
Reset States
PIEJ[7:6],[3:0]
Local Enable
PIEG[7:0]
PIEH[6:0]
Wired-Or
disabled
disabled
Mode
n/a
n/a
n/a
n/a
n/a
Global (CCR)
Mask
I Bit
I Bit
I Bit
Interrupt
disabled
disabled
disabled
disabled
n/a
n/a
n/a
Interrupts
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