MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 382

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.2.2.2 VDDA, VSSA - Regulator Reference Supply
Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts
of the regulator. Internal precision reference circuits are supplied from these signals. A chip
external decoupling capacitor (100nF...220nF, X7R ceramic) between VDDA and VSSA can
further improve the quality of this supply.
13.2.2.3 VDD, VSS - Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG_PHY that provide the power supply for the
core logic. These signals are connected to device pins to allow external decoupling capacitors
(100nF...220nF, X7R ceramic).
In Shutdown Mode an external supply at VDD/VSS can replace the voltage regulator.
13.2.2.4 VDDPLL, VSSPLL - Regulator Output2 (PLL)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_PHY that provide the power
supply for the PLL and Oscillator. These signals are connected to device pins to allow external
decoupling capacitors (100nF...220nF, X7R ceramic).
In Shutdown Mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.
13.2.2.5 VDDAUX1,2,3, VSSAUX1,2,3 - Regulator Output3,4,5
Signals VDDAUX1,2,3/VSSAUX1,2,3 are the auxilliary outputs of VREG_PHY. These signals
are connected to device pins to allow external decoupling capacitors (100nF...220nF, X7R
ceramic).
In Shutdown Mode an external supply at VDDAUX1,2,3/VSSAUX1,2,3 can replace the voltage
regulator.
13.2.2.6 VREGEN - Optional Regulator Enable
This optional signal is used to shutdown VREG_PHY. In that case VDD/VSS and
VDDPLL/VSSPLL must be provided externally. Shutdown Mode is entered with VREGEN
being low. If VREGEN is high, the VREG_PHY is either in Full Performance Mode or in Reduced
Power Mode.
For the connectivity of VREGEN see device specification.
NOTE
Switching from FPM or RPM to shutdown of VREG_PHY and vice
versa is not supported while MCU is powered.
MC9S12NE64 Data Sheet, Rev. 1.1
382
Freescale Semiconductor