MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 370

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
If the auto-negotiation mode of operation is desired, the ANDIS bit in the EPHYCTL0 must be set to 0
and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. Refer to
“Auto-Negotiation,”
If the mode of operation will be set manually, the ANDIS bit must be set to 1 in the EPHYCTL0 register
and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. After the EPHYEN bit has
been set and the start-up delay period is completed, the mode of operation can be configured through the
MII registers.
12.4.2
Auto-negotiation is used to determine the capabilities of the link partner. Auto-negotiation is compliant
with IEEE 802.3 clause 28. In this case, the PHY will transmit fast link pulse (FLP) bursts to share its
capabilities with the link partner.
If the link partner is also capable of performing auto-negotiation, it will also send FLP bursts. The
information shared through the FLP bursts will allow both link partners to find the highest common mode
(if it exists).
If no common mode is found, the remote fault bit (1.4) will be set. A remote fault is defined as a condition
in which the PHY and the link partner cannot establish a common operating mode. Configuring
auto-negotiation advertisement register sets the different auto-negotiation advertisement modes.
If the link partner does not support auto-negotiation, it will transmit either normal link pulses (NLP) for
10 Mbps operation, or 100 Mbps idle symbols. Based on the received signal, the PHY determines whether
the link partner is 10 Mbps capable or 100 Mbps capable. The ability to do this is called parallel detection.
If using parallel detection, the link will be configured as a half-duplex link. After parallel detection has
established the link configuration, the remote fault bit will be set if the operating mode does not match the
pre-set operating modes.
370
1
Bit 0.12
Symbol mode is not supported.
Auto
Neg.
0
0
0
0
0
0
0
0
Auto-Negotiation
Table 12-3
Bit 0.13
Table 12-3. Operational Configuration While Auto-Negotiation is Disabled
Data
Rate
0
0
1
1
1
1
1
1
for more information on auto-negotiation operation.
Duplex
summarizes the MII register configuration and operational modes.
Bit 0.8
1
0
1
1
1
1
1
0
Encoder
Bit 18.6
Bypass
MC9S12NE64 Data Sheet, Rev. 1.1
X
X
0
1
1
1
1
0
Scrambler
Bit 18.5
Bypass
X
X
0
0
0
1
1
0
Symbol
Unalign
Bit 18.7
X
X
0
0
1
0
1
0
10BASE-T full-duplex
10BASE-T half-duplex
100BASE-TX full-duplex
100BASE-TX full-duplex with encoder
bypass (symbol mode) — aligned
100BASE-TX full-duplex with encoder
bypass (symbol mode) — unaligned
100BASE-TX full-duplex with scrambler
and encoder bypassed (symbol mode),
aligned
100BASE-TX full-duplex with scrambler
and encoder bypassed (symbol mode),
unaligned
100BASE-TX half-duplex
Operation
Freescale Semiconductor
Section 12.4.2,
1