MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 389

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

14.3
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
14.3.1
14.3.2
14.3.2.1
Read: See individual bit descriptions
Write: See individual bit descriptions
Freescale Semiconductor
ADR[3:0]
WRTINT
Reset
Field
3:0
4
W
R
Memory Map and Register Definition
Address
0x0015
0x0016
0x001F
Offset
Module Memory Map
Register Descriptions
Write to the Interrupt Test Registers
Read: anytime
Write: only in special modes and with I-bit mask and X-bit mask set.
0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.
1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers
Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.
Test Register Select Bits
Read: anytime
Write: anytime
These bits determine which test register is selected on a read or write. The hexadecimal value written here will
be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR[3:0] will
select vectors 0xFFFE–0xFFF0 while a “7” written to ADR[3:0] will select vectors 0xFF7E–0xFF70.
Interrupt Test Control Register
0
0
7
instead.
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
= Unimplemented or Reserved
0
0
6
Figure 14-2. Interrupt Test Control Register (ITCR)
Table 14-2. ITCR Field Descriptions
MC9S12NE64 Data Sheet, Rev. 1.1
0
0
5
Table 14-1. INT Memory Map
WRTINT
0
4
Use
Description
ADR3
1
3
ADR2
1
2
Memory Map and Register Definition
ADR1
1
1
Access
R/W
R/W
R/W
ADR0
1
0
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