MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 315

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

RXACT — Receiver Active Status
RFCE — Reception Flow Control Enable
PROM — Promiscuous Mode
CONMC — Conditional Multicast
BCREJ — Broadcast Reject
Freescale Semiconductor
This is a read-only status bit that indicates activity in the EMAC receiver. RXACT is asserted when
MII_RXDV is asserted and clears when the EMAC has finished processing the receive frame after
MII_RXDV is negated.
This bit can be written anytime, but the user must not change this bit while EMACE is set.
While this bit is set, the receiver detects PAUSE frames (full-duplex mode only). Upon PAUSE frame
detection, the transmitter stops transmitting data frames for a given duration (PAUSE time in received
frame). The value of the PAUSE timer counter is updated when a valid PAUSE control frame is
received.
While this bit is clear, the receiver ignores any PAUSE frames.
This bit can be written anytime, but the user must not change this bit while EMACE is set. Changing
values while the receiver is active may affect the outcome of the receive filters.
While set, the address recognition filter is ignored and all frames are received regardless of destination
address.
While clear, the destination address is checked for incoming frames.
This bit can be written anytime, but the user must not change this bit while EMACE is set. Changing
values while the receiver is active may affect the outcome of the receive filters.
While set, the multicast hash table is used to check all multicast addresses received unless the PROM
bit is set.
While clear, all multicast address frames are accepted.
This bit can be written anytime, but the user must not change this bit while EMACE is set.
While set, all broadcast addresses are rejected unless the PROM bit is set.
While clear, all broadcast address frames are accepted.
1 = Receiver is active.
0 = Receiver is idle.
1 = Upon PAUSE frame detection, transmitter stops for a given duration.
0 = Received PAUSE control frames are ignored.
1 = All frames are received regardless of address.
0 = Destination address is checked for incoming frames.
1 = Multicast hash table is used for checking multicast addresses.
0 = Multicast address frames are accepted.
1 = All broadcast address frames are rejected.
0 = All broadcast address frames are accepted.
MC9S12NE64 Data Sheet, Rev. 1.1
Memory Map and Register Descriptions
315