MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 323

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.10 MII Management PHY Address (MPADR)
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
PADDR — MII Management PHY Address
11.3.2.11 MII Management Register Address (MRADR)
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
RADDR — MII Management Register Address
11.3.2.12 MII Management Write Data (MWDATA)
Module Base + $12
Read: Anytime.
Write: Anytime, but the user must not change this field while BUSY is set.
Freescale Semiconductor
RESET:
W
This field specifies 1 of up to 32 attached PHY devices. The default address for the internal PHY after
reset is 0, but can be changed by writing the PHY address register.
This field selects 1 of the 32 MII registers of a PHY device to be accessed. The default address for the
internal PHY after reset is 0, but can be changed by writing the PHY address register.
R
Module Base + $10
Module Base + $11
RESET:
RESET:
W
W
R
R
15
0
14
0
7
0
0
7
0
0
13
0
Figure 11-12. MII Management Register Address (MRADR)
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 11-11. MII Management PHY Address (MPADR)
Figure 11-13. MII Management Write Data (MWDATA)
12
0
6
0
0
6
0
0
11
0
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
0
5
0
0
10
0
9
0
4
0
4
0
8
0
WDATA
7
0
3
0
3
0
6
0
RADDR
PADDR
2
0
2
0
5
0
Memory Map and Register Descriptions
4
0
1
0
1
0
3
0
2
0
0
0
0
0
1
0
0
0
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