MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 362

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
Message/Unformatted Code Field
12.3.3.8 Auto-Negotiation Expansion Register
Figure 12-13
This register contains information about the A/N capabilities of the port’s link partner and information on
the status of the parallel detection mechanism.
MII Register Address 6 (%00110)
Read: Anytime
Write: Never
PDFLT — Parallel Detection Fault
LPNPA — Link Partner Next Page Able
NXTPA — Next Page Able
PRCVD — Page Received
362
RESET:
W
Message code field — Predefined code fields defined in IEEE 802.3u-1995 Annex 28C
Unformatted code filed — 11-bit field containing an arbitrary value
This bit is used to indicate that zero or more than one of the NLP receive link integrity test function
for 100BASE-TX have indicated that the link is ready (link_status=READY) when the A/N wait timer
has expired. PDFLT will be reset to 0 after a read of register 6.
Bit to indicate whether the link partner has the capability of using NP.
This bit is used to inform the MI and the link partner whether the port has next page capabilities.
Bit is used to indicate whether a new link code word has been received and stored in the A/N link
partner ability register (MII register 5). PRCVD is reset to 0 after register 6 is read.
R
1 = Parallel detection fault has occurred
0 = Parallel detection fault has not occurred
1 = Link partner is next page able
0 = Link partner is not next page able
1 = The port has next page capabilities
0 = The port does not have next page capabilities
1 = Three identical and consecutive link code words have been received from link partner
0 = Three identical and consecutive link code words have not been received from link partner
15
0
0
shows the contents of the A/N expansion register. The MI process can only read this register.
= Unimplemented or Reserved
14
0
0
13
0
0
Figure 12-13. Auto-Negotiation Expansion Register
12
0
0
11
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
PDFLT LPNPA NXTPA PRCVD LPANA
4
0
3
0
Freescale Semiconductor
2
1
1
0
0
0