MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 65

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

1.7.3
See the CRG chapter for information about the clock and reset generator module. For the MC9S12NE64,
only the Pierce circuitry is available for the oscillator.
The low-voltage reset feature uses the low-voltage reset signal from the VREG_PHY module as an input
to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a
specified threshold, the LVR signal from the VREG_PHY module causes the CRG module to generate a
reset. See the VREG_PHY block description chapter for voltage level specifications.
1.7.4
See the OSC chapter for information about the oscillator module. The XCLKS input signal is not available
on the MC9S12NE64. The signal is internally tied low to select the Pierce oscillator or external clock
configuration.
1.7.5
See the EMAC chapter for information about the Ethernet media access controller module. The EMAC is
part of the IPBus domain.
1.7.5.1
When the EMAC is configured for and external Ethernet physical transceiver internal pull-ups and
pull-downs are not automatically configured on the MII inputs. Any internal pull-up or pull-down resistors,
which may be required, must be configured by setting the appropriate pull control registers in the port
integration module (PIM). This implementation allows the use of external pull-up and pull-down resistors.
1.7.5.2
When the EXTPHY bit (in the EMAC NETCTL register) is set to 1, the EMAC is configured to work with
the internal EPHY block. Please see
regarding the EPHY block.
1.7.5.3
Special care must be taken when executing STOP and WAIT instructions while using the EMAC, or
undesired operation may result.
1.7.5.3.1
Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL
register because the clocks to the transmit and receive buffers are stopped. It is recommended that the
EMAC ESWAI bit be set if wait mode is entered with the CWAI set.
Freescale Semiconductor
Clock Reset Generator (CRG)
Oscillator (OSC)
Ethernet Media Access Controller (EMAC)
EMAC MII External Pin Configuration
EMAC Internal PHY Configuration
Low-Power Operation
Wait
1.7.6, “Ethernet Physical Transceiver
MC9S12NE64 Data Sheet, Rev 1.0
(EPHY),” for more information
Block Configuration for MC9S12NE64
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