MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 352

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
ANDIS — Auto Negotiation Disable
DIS100 — Disable 100 BASE-TX PLL
DIS10 — Disable 10BASE-T PLL
LEDEN — LED Drive Enable
EPHYWAI — EPHY Module Stops While in Wait
EPHYIEN — EPHY Interrupt Enable
12.3.2.2 Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
352
This bit can be written anytime, but the value is latched in the ANE bit of the MII PHY control register
(MII address 0.12) only when the EPHYEN bit transitions from 0 to 1.
This bit can be written anytime. Allows user to power down the clock generation PLL for
100BASE-TX clocks.
This bit can be written anytime. Allows user to power down the clock generation PLL for 10BASE-T
clocks.
This bit can be written anytime.
This bit can be written anytime.
This bit can be written anytime.
1 = Auto negotiation is disabled after start-up. A 0 is latched in the ANE bit of the MII PHY control
0 = Auto negotiation is enabled after start-up. A 1 is latched in the ANE bit of the MII PHY control
1 = Disables 100BASE-TX PLL
0 = 100BASE-TX PLL state determined by EPHY operation mode
1 = Disables 10BASE-T PLL
0 = 10 BASE-T PLL state determined by EPHY operation mode
1 = Enables the EPHY to drive LED signals.
0 = Disables the EPHY to drive LED signals.
1 = Disables the EPHY module while the MCU is in wait mode. EPHY interrupts cannot be used
0 = Allows the EPHY module to continue running during wait.
1 = Enables EPHY module interrupts
0 = Disables EPHY module interrupts
Module Base + $1
RESET:
W
R
register (MII address 0.12), and upon completion of the start-up delay (t
bypass auto-negotiation. The mode of operation will be determined by the manual setting of
MII registers.
register (MII address 0.12), and upon completion of the start-up delay (t
enter auto-negotiation. The mode of operation will be automatically determined.
to bring the MCU out of wait.
Figure 12-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
7
0
0
= Unimplemented or Reserved
6
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
0
PHYADD4 PHYADD3 PHYADD2 PHYADD1 PHYADD0
4
0
3
0
2
0
Start-up
Start-up
1
0
Freescale Semiconductor
), the EPHY will
), the EPHY will
0
0