MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 320

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Ethernet Media Access Controller (EMACV1)
RXEIF — Receive Error Interrupt Flag
RXAOIF — Receive Buffer A Overrun Interrupt Flag
RXBOIF — Receive Buffer B Overrun Interrupt Flag
RXACIF — Valid Frame Reception to Receive Buffer A Complete Interrupt Flag
RXBCIF — Valid Frame Reception to Receive Buffer B Complete Interrupt Flag
MMCIF — MII Management Transfer Complete Interrupt Flag
LCIF — Late Collision Interrupt Flag
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This flag is set when MII_RXER signal is asserted during reception, when there is a receive frame
length mismatch, an alignment error, or when a CRC error has occurred. If not masked (RXEIE is set),
a receive error interrupt is pending while this flag is set.
This flag is set when an overrun occurs in receive buffer A. If not masked (RXAOIE is set), a receive
buffer A overrun interrupt is pending while this flag is set.
This flag is set when an overrun occurs in receive buffer B. If not masked (RXBOIE is set), a receive
buffer B overrun interrupt is pending while this flag is set.
This flag is set when a complete valid frame has been received in receive buffer A. If not masked
(RXACIE is set), a valid frame reception to receive buffer A complete interrupt is pending while this
flag is set.
This flag is set when a complete valid frame has been received in receive buffer B. If not masked
(RXBCIE is set), a valid frame reception to receive buffer B complete interrupt is pending while this
flag is set.
This flag is set when the MII has completed a requested MII management transfer. If not masked
(MMCIE is set), an MII management transfer complete interrupt is pending while this flag is set.
This flag is set if a collision has occurred after the collision window of 512 bit times while in
half-duplex mode. If not masked (LCIE is set), a late collision interrupt is pending while this flag is set.
1 = Receive errors have been detected.
0 = No receive errors have been detected.
1 = Receive buffer A overrun has occurred.
0 = No receive buffer A overrun has been detected.
1 = Receive buffer B overrun has occurred.
0 = No receive buffer B overrun has been detected.
1 = Frame to receive buffer A has been validated.
0 = Frame to receive buffer A has not been validated.
1 = Frame to receive buffer B has been validated.
0 = Frame to receive buffer B has not been validated.
1 = MII management transfer completion.
0 = MII management transfer in progress or none requested.
1 = Late collision during transmission.
0 = No collisions after collision window.
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor