MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 56

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 1 MC9S12NE64 Device Overview
1.2.3.52 PS2 / SCI1_RXD — Port S I/O Pin 2
PS2 is a general-purpose I/O. When the serial communications interface 1 (SCI1) receiver is enabled, PS2
becomes the receive pin RXD of SCI1. While in reset and immediately out of reset, the PS2 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.53 PS1 / SCI0_TXD — Port S I/O Pin 1
PS1 is a general-purpose I/O. When the serial communications interface 0 (SCI0) transmitter is enabled,
PS1 becomes the transmit pin, TXD, of SCI0. While in reset and immediately out of reset, the PS1 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.54 PS0 / SCI0_RXD — Port S I/O Pin 0
PS0 is a general-purpose I/O. When the serial communications interface 0 (SCI0) receiver is enabled, PS0
becomes the receive pin RXD0 of SCI0. While in reset and immediately out of reset, the PS0 pin is
configured as a high-impedance input pin. See the port integration module (PIM) PIM_9NE64 block
description chapter and the SCI block description chapter for information about pin configurations.
1.2.3.55 PT[7:4] / IOC1[7:4] — Port T I/O Pins [7:4]
PT[7:4] are general-purpose I/O pins. While the timer system 1 (TIM1) is enabled, these pins can also be
configured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and immediately
out of reset, the PT[7:4] pins are configured as a high-impedance input pins. See the port integration
module (PIM) PIM_9NE64 block description chapter and the TIM_16B4C block description chapter for
information about pin configurations.
1.2.3.56 PHY_TXP — EPHY Twisted Pair Output +
Ethernet twisted pair output pin. This pin is hi-z out of reset.
1.2.3.57 PHY_TXN — EPHY Twisted Pair Output –
Ethernet twisted pair output pin. This pin is hi-z out of reset.
1.2.3.58 PHY_RXP — EPHY Twisted Pair Input +
Ethernet twisted pair input pin. This pin is hi-z out of reset.
1.2.3.59 PHY_RXN — EPHY Twisted Pair Input –
Ethernet twisted pair input pin. This pin is hi-z out of reset.
MC9S12NE64 Data Sheet, Rev 1.0
56
Freescale Semiconductor