MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 473

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

18.2
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching
on the external bus.
The tag pins in
Freescale Semiconductor
PE3/LSTRB/ TAGLO
BKGD/MODC/
CPU PROGRAM COUNTER
INSTRUCTION
Pin Name
LAST CYCLE
BUS CLOCK
TAGHI
External Signal Description
WRITE DATA BUS
READ DATA BUS
ADDRESS BUS
WRITE DATA BUS
READ DATA BUS
READ/WRITE
DBG MODE ENABLE
CHANGE-OF-FLOW
INDICATORS
MCU IN BDM
DBG READ DATA BUS
Table 18-1
READ/WRITE
REGISTER
Table 18-1. External System Pins Associated with DBG and MEBI
Pin Functions
TAGLO
TAGHI
(part of the MEBI) may also be a part of the breakpoint operation.
Figure 18-2. DBG Block Diagram in DBG Mode
M
U
X
When instruction tagging is on, a 0 at the falling edge of E tags the high half of the
instruction word being read into the instruction queue.
In expanded wide mode or emulation narrow modes, when instruction tagging is on
and low strobe is enabled, a 0 at the falling edge of E tags the low half of the
instruction word being read into the instruction queue.
M
U
X
MC9S12NE64 Data Sheet, Rev. 1.1
INSTRUCTION
ADDRESS/DATA/CONTROL
ADDRESS
M
U
X
COMPARATOR A
COMPARATOR B
COMPARATOR C
LAST
REGISTERS
64 x 16 BIT
REGISTER
CAPTURE
PROFILE
BUFFER
TRACE
WORD
Description
CONTROL
MATCH_A
MATCH_B
MATCH_C
LOOP1
EVENT ONLY
POINTER
M
U
X
STORE
DETAIL
PROFILE CAPTURE MODE
CONTROL
TRACER
OR PROFILING DATA
BUFFER
External Signal Description
LOGIC
TRACE BUFFER
TAG
FORCE
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