MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 77

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

2.3.2.5
The FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only
readable (see
During reset, the FPROT register is loaded from the Flash Configuration Field at address 0xFF0D. To
change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash
memory must be unprotected, then the Flash Protect/Security byte located as described in
be reprogrammed.
Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error
and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if
any of the contained Flash sectors are protected.
Freescale Semiconductor
FPHS[1:0]
FPOPEN
KEYACC
FPHDIS
RNV[6]
Field
CCIE
Field
4:3
6
5
7
6
5
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
Protection Function Bit — The FPOPEN bit determines the protection function for program or erase as shown
in
0 FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0]
1 FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0]
Reserved Nonvolatile Bit — The RNV[6] bit must remain in the erased state 1 for future enhancements.
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in the higher address space of the Flash block.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected
area as shown in
Flash Protection Register (FPROT)
Section 2.3.2.6, “Flash Protection
Table
is set.
data.
and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part
of the Flash block to be protected while a small address range can remain unprotected for EEPROM
emulation.
and FPLS[1:0] bits.
2-10.
Table
Table 2-8. FCNFG Field Descriptions (continued)
2-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.
Table 2-9. FPROT Field Descriptions
MC9S12NE64 Data Sheet, Rev. 1.1
Restrictions”).
Description
Description
Section 2.3.2.7, “Flash Status Register
Memory Map and Register Definition
Table 2-1
(FSTAT)”)
must
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