IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
12.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU
while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and
timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in
Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in
active mode before entering Idle. Stop mode consumes the least power. Figure 12.15 describes the Power Control
Register (PCON) used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog periph-
eral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses,
draw little power whenever they are not in use. Turning off the Flash memory saves power, similar to entering Idle
mode. Turning off the oscillator saves even more power, but requires a reset to restart the MCU.
12.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog and
digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt
will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction
immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external
reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This fea-
ture protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON
register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the
WDT was initially configured to allow this operation. This provides the opportunity for additional power savings,
allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system.
Refer to
Section “13.8. Watchdog Timer Reset” on page 129
for more information on the use and configuration of
the WDT.
12.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes. In Stop mode, the CPU and internal oscillator are stopped, effectively shutting down all digital
peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can only
be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins
program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing
Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs.
Rev. 1.4
125