IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 75/272

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7.
ADC1 (8-BIT ADC)
The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1),
a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold (see block diagram in Figure 7.1). The AMUX1, PGA1, and Data Conversion Modes, are all
configurable under software control via the Special Function Registers shown in Figure 7.1. The ADC1 subsystem
(8-bit ADC, track-and-hold and PGA) is enabled only when the AD1EN bit in the ADC1 Control register (ADC1CN)
is set to logic 1. The ADC1 subsystem is in low power shutdown when this bit is logic 0. The voltage reference used
by ADC1 is selected as described in
C8051F020/2 devices, or
Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93
devices.
Figure 7.1. ADC1 Functional Block Diagram
AIN1.0 (P1.0)
AIN1.1 (P1.1)
AIN1.2 (P1.2)
AIN1.3 (P1.3)
8-to-1
AMUX
AIN1.4 (P1.4)
AIN1.5 (P1.5)
AIN1.6 (P1.6)
AIN1.7 (P1.7)
7.1.
Analog Multiplexer and PGA
Eight ADC1 channels are available for measurement, as selected by the AMX1SL register (see Figure 7.5). The PGA
amplifies the ADC1 output signal by an amount determined by the states of the AMP1GN2-0 bits in the ADC1 Con-
figuration register, ADC1CF (Figure 7.4). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain
defaults to 0.5 on reset.
Important Note: AIN1 pins also function as Port 1 I/O pins, and must be configured as analog inputs when used as
ADC1 inputs. To configure an AIN1 pin for analog input, set to ‘0’ the corresponding bit in register P1MDIN. Port 1
pins selected as analog inputs are skipped by the Digital I/O Crossbar. See
as Analog Inputs (AIN1.[7:0])” on page 165
Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91
AV+
AD1EN
AV+
8-Bit
+
SAR
X
-
ADC
AGND
ADC1CF
AMX1SL
ADC1CN
Section “17.1.6. Configuring Port 1 Pins
for more information on configuring the AIN1 pins.
Rev. 1.4
C8051F020/1/2/3
for
for C8051F021/3
8
000
Write to AD1BUSY
001
Timer 3 Overflow
Start Conversion
010
CNVSTR
011
Timer 2 Overflow
Write to AD0BUSY
1xx
(synchronized with
ADC0)
75